Category: UVM

A recent Accellera meeting (end of Sept 2010) on UVM voted to incorporate a heavily modifed version of Synopsys' RAL package (Register Abstraction Layer) into UVM1.0 for register and memory verification. A typical design contains hundreds, if not thousan… more »

OVM has recently suffered from the lack of a good, up-to-date textbook. So it's good news to see that UVM now has a great textbook written by the verification experts at Cadence.   A Practical Guide to Adopting the Universal Verification Methodology (UVM… more »

Esperan has just released it's UVM training class - SystemVerilog Advanced Verification using UVM1.0ea. This is a version of our hugely popular OVM training, adapted to use the Accellera's Early Adopter version of UVM library. If you are new to SystemV… more »

The first official release of UVM 1.0 EA (early adopter) kit is now available from the Accellera web site. The main difference between UVM1.0EA and OVM2.1.1 is to rename all ovm_* identifiers to uvm_* . More specifically the renaming is as follows:-… more »

The Accellera committee responsible for defining the new UVM standard have had a change of mind, and have formally voted to base UVM on the latest release of the OVM library, version 2.1.1, rather than OVM2.0.3 which was the original decision.This is a… more »