Category: OVM

A recent Accellera meeting made some important decisions about the direction and future of the UVM1.0 standard, the proposed Accellera replacement for OVM and VMM. For VMM users, there is only good news - they can finally migrate to a standard SystemVeri… more »

Subsequent to yesterday's UVM post, a kind soul sent me a link to the official Accellera update on UVM (PDF), and it makes interesting reading. Follow up:Some key points:- UVM will be based on OVM2.0.3, although hopefully they will include some o… more »

Accellera has stepped into the SystemVerilog verification class library war between Cadence/Mentor's Open Verification Methodology (OVM) and Synopsys' Verification Methodology Manual (VMM), by announcing plans to release a Universal Verification Methodol… more »

If you're an Emacs fan, then you're probably familiar with the popular verilog_mode which now supports SystemVerilog and OVM. You may also be familar with the yasnippet template system for Emacs, allowing you to type simple abbreviations and expand them… more »

Following the tutorial on Customized Printing in OVM, lets take a look at customizing the output of print_topology() in OVM.Follow up:There are some useful ovm_printer_knobs for topology printing, for example depth. This controls the recursion de… more »