Tech Blog

UVM Textbook on Kindle!

brian — Tue, 28 Sep 2010 13:35:22 +0000

The new UVM textbook, A Practical Guide to Adopting the Universal Verification Methodology (UVM), is now available on Kindle. Obviously there are some concerns about how the formatting and figures will appear on the device, but according to several users, the book is quite readable. If you own a kindle, you should be able to preview pages of this book for free.

Original post blogged on b2evolution.

Register and Memory Modelling in UVM1.0

brian — Tue, 28 Sep 2010 13:22:01 +0000

A recent Accellera meeting (end of Sept 2010) on UVM voted to incorporate a heavily modifed version of Synopsys' RAL package (Register Abstraction Layer) into UVM1.0 for register and memory verification. A typical design contains hundreds, if not thousands of registers and memory blocks, the configuration of which is essential to the correct functionality of the design. Capturing the characteristics of these registers, and checking their behaviour, is a key part of design verification.

Original post blogged on b2evolution.

UVM Text Book Released!

brian — Wed, 21 Jul 2010 22:27:49 +0000

OVM has recently suffered from the lack of a good, up-to-date textbook. So it's good news to see that UVM now has a great textbook written by the verification experts at Cadence. A Practical Guide to Adopting the Universal Verification Methodology (UVM) is both a valuable reference for novices and an impressive treasury of verification knowledge for experts. It's also pitched at a good price for a technical textbook. Having had a sneak preview of the contents, I recommend you rush out and buy a copy before the first print run sells out - which it will do, fast. We hope to bring you a in-depth review of this book as soon as they start shipping.

Original post blogged on b2evolution.

UVM and OVM training

brian — Wed, 21 Jul 2010 22:10:52 +0000

Esperan has just released it's UVM training class - SystemVerilog Advanced Verification using UVM1.0ea. This is a version of our hugely popular OVM training, adapted to use the Accellera's Early Adopter version of the UVM library.

If you are new to SystemVerilog Verification, or are considering transitioning to UVM, then we recommend the UVM training class.

If, however, you are existing OVM users, then the current OVM class may be preferable.

At the moment, since UVM1.0 = OVM2.1, it is possible to take either the OVM or UVM class and be able to write verification environments with either library. However, as future development is concentrated on UVM, we expect significant differences to start to appear between OVM and UVM training by the end of the year.

Original post blogged on b2evolution.

UVM 1.0 released

brian — Mon, 17 May 2010 19:57:02 +0000

The first official release of UVM 1.0 EA (early adopter) kit is now available from the Accellera web site. The main difference between UVM1.0EA and OVM2.1.1 is to rename all ovm_* identifiers to uvm_* .

More specifically the renaming is as follows:-

ovm_ replaced with uvm_
OVM_ replaced with UVM_
tlm_ replaced with uvm_tlm_
TLM_ replaced with UVM_TLM_

and yes - there is a script in the kit to do this automatically.

There's a couple of other things to watch out for if you try using this release:-

Original post blogged on b2evolution.

UVM1.0 Update - to be based on OVM2.1.1

brian — Mon, 03 May 2010 15:22:44 +0000

The Accellera committee responsible for defining the new UVM standard have had a change of mind, and have formally voted to base UVM on the latest release of the OVM library, version 2.1.1, rather than OVM2.0.3 which was the original decision.

This is a good decision from Accellera and great news for existing OVM users. Engineers can now use the new features of OVM2.1 (objection mechanisms, callbacks etc) with the knowledge that they will work in UVM. Needless to say there has been a fair amount of relief on the Cadence and Mentor verification blogs.

So the bottom line, as aptly defined by Tom Anderson from Cadence, is that "UVM = OVM" now, but with the Accellera committee moving onto new features and technology, we fully expect "UVM > OVM". His blog post is well worth a visit.

Original post blogged on b2evolution.

OVM2.1.1 Released

brian — Mon, 03 May 2010 15:22:22 +0000

OVM2.1.1 has been released. There are few new features in this release, it is mainly a bug-fix for OVM2.1, particularly in the areas of reporting and the objection mechanism. The new release is available from OVM World and the release notes list all the bug, documentation and miscellaneous fixes.

Original post blogged on b2evolution.

UVM1.0 - the good news and the bad news...

brian — Mon, 03 May 2010 15:22:00 +0000

A recent Accellera meeting made some important decisions about the direction and future of the UVM1.0 standard, the proposed Accellera replacement for OVM and VMM.

For VMM users, there is only good news - they can finally migrate to a standard SystemVerilog class library. For existing OVM users however, there's some good news and some bad news..Read more »

Original post blogged on b2evolution.