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Register and Memory Modelling in UVM1.0

28/09/10 | by brian [mail] | Categories: SystemVerilog, UVM

A recent Accellera meeting (end of Sept 2010) on UVM voted to incorporate a heavily modifed version of Synopsys' RAL package (Register Abstraction Layer) into UVM1.0 for register and memory verification. A typical design contains hundreds, if not thousands of registers and memory blocks, the configuration of which is essential to the correct functionality of the design. Capturing the characteristics of these registers, and checking their behaviour, is a key part of design verification.

Follow up:

Currently the big three vendors have their own Register Modelling packages. Mentor has OVM_REGISTER, Cadence has OVM_RGM which has already been converted for UVM (UVM_RGM) and Synopsys has RAL for VMM.

 

Although Accellera has voted to adopt RAL, the package obviously requires significant work to run natively on the UVM base library. This development, with consequent evaluation and testing, is still ongoing. Therefore the package is not yet available.  Indeed, such are the modifications required to the RAL package for UVM compatibility, that it seems even existing RAL users will be rewriting their code to use the new package.

 

So  every existing Register package user will have to rewrite their code for compatibility with a new package. Not the best situation for the UVM community.  Accellera have much work to do in developing and testing the new proposed package in time for the full UVM1.0 release in November.

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