Accellera has stepped into the SystemVerilog verification class library war between Cadence/Mentor's Open Verification Methodology (OVM) and Synopsys' Verification Methodology Manual (VMM), by announcing plans to release a Universal Verification Methodology (UVM) standard.

Follow up:

Although this may finally give us a single standard for SystemVerilog verification, many OVM and VMM users are, understandably, looking nervously at their working environments and wondering if all this code will have to change when UVM is released. Good news for OVM users is that UVM will be based on OVM, although full backwards compatibility may be too much to hope for...

Personally I think Accellera have set themselves a really tough task here. They are working to insanely tight deadlines (UVM release is projected for March 2010). OVM has set the bar high with Open-Source code, third-party contributions and a huge community of users. Although a standard library may be a high priority for the big, multi-vendor design companies, the SME's may not be so enthusiastic about yet another class library.

Gabe Moretti has a good summary of the issues on his blog.